Low-voltage differential signaling (LVDS) is a differential interconnectivity standard. It uses a low voltage swing of approximately 350 mV to communicate over a pair of traces on a PCB or cable.
Electronic devices that require high speed communications, either internally or with other devices, use LVDS drivers extensively. Moving high-bandwidth digital video data, for example, within modern consumer appliances and between them is a very challenging task. This requires the speed that low power LVDS offers.
Traditional LVDS drivers typically have architectures that require operational amplifiers (op-amps) to produce the voltages that control the current from two current sources and logic-controlled switches determine the direction of the current across a load. The direction of the current across the load determines the LVDS signal polarity. LVDS load and signaling levels are specified by standards such as the TIA/EIA-644 standard. The current source, supply voltage, switches and op-amp bandwidth, in addition to the time constant of the LVDS load, determine the maximum speed of the driver. The swing and common mode voltage are difficult to control and maintain over carriers.
Conventional art FIG. 1 illustrates an exemplary LVDS driver using operational amplifiers (op-amps). Op-amps 101 and 102 typically control the current through driver 100 by controlling the current flow through current supplies 103 and 104. Logical switches 108 and 110 control the current flow direction through LVDS load 105, in this example a resistor, in order to produce a voltage across the load. That voltage, at nodes 120 and 121, must meet the LVDS specification. such as that in the TIA/EIA-644 standard referred to above. It is noted that the standard also includes maximum of 5 pF for parasitic capacitance, as shown at 106.
Op-amp structures, particularly, have had an impact on device speeds. With currently available process technologies, an op-amp which steers current sources on the low side of a driven signal must utilize complex topologies to be used in a 1.8V system. This is mandated by the 1.2V common-mode LVDS requirement when the supply voltage is 1.8V. This forces the design of the op-amp to be a multi-pole system and stability becomes a concern.
The output impedance of a typical LVDS structure is a sum of switch resistances and an LVDS load resistor, specified in the standard as 100 ohms, and LVDS load capacitance is specified at no more than 5 pF. This results in a significant RC delay that limits the maximum speed available for any given supply power.
Modern LVDS signaling specifications require a relatively high voltage power supply, e.g., on the order of 2.5-3V. With emerging chip technologies enabling sub-1.8V power supplies, building high-speed, TIA complaint, LVDS circuits becomes a challenge. Many chips have implemented split rail architectures to enable larger input/output (I/O) voltages. Traditional architectures, though, have not been able to take advantage of the emerging low power supply technologies. This has become even more important as power supplies have continued to shrink.
By requiring op-amps to control the current sources, the flexibility or programmability of the traditional driver architecture has been limited to the input characteristics of the op-amps. This does not enable most traditional LVDS drivers to be used at multiple power supply voltages and the tradeoff of power versus speed is not adjustable with existing architectures.